CINTMK=0, SFT=00, BLERRD=0, STERRD=0, CDFC=0, CESEL=00
CEC Control Register 1
| SFT | Signal-Free Time Data Bit Width Select 0 (00): 3-data bit width 1 (01): 5-data bit width 2 (10): 7-data bit width 3 (11): Does not detect signal-free time. |
| CESEL | Communication Complete Interrupt (INTCE) Generation Timing Select 0 (00): Generates communication complete interrupt once after ACK transmission (reception) of the last frame (EOM = 1) is complete and another time after signal-free time is detected. 1 (01): Generates communication complete interrupt after ACK transmission (reception) of the last frame (EOM = 1) is completed. 2 (10): Generates communication complete interrupt after signal-free time is detected. 3 (11): Setting prohibited |
| STERRD | Start Bit Error Detection Select 0 (0): Does not detect timing errors during start bit reception. 1 (1): Detects timing errors during start bit reception. |
| BLERRD | Bus Lock Detection Select 0 (0): Does not detect sticking of receive data to high or low 1 (1): Detects sticking of receive data to high or low. |
| CINTMK | CEC Data Interrupt (INTDA) Generation Select 0 (0): Does not generate an interrupt when the addresses do not match. 1 (1): Generates an interrupt when the addresses do not match. |
| CDFC | Digital Filter Select 0 (0): Does not use a digital filter. 1 (1): Uses a digital filter. |